A flash memory cell may have a double polysilicon structure such that information can be stored in and deleted from a specific cell.
FIG. 1 illustrates an Electrically Erasable Programmable Read Only Memory (EEPROM) or a flash memory cell having a double polysilicon structure in a memory block.
As illustrated in FIG. 1, a flash memory cell of a double polysilicon structure has tunnel oxide film 12, floating gate 14, dielectric film 16, control gate 18, source region 20, spacer 22, and the like formed in that order on and/or over semiconductor substrate 10. Accordingly, such a flash memory cell has two gates: floating gate 14 and control gate 18. Floating gate 14 and control gate 18 are separated from each other by dielectric film 16. Floating gate 14 and semiconductor substrate 10 are separated from each other by tunnel oxide film 12.
In such a flash memory, data storage is implemented by injecting electrons or holes into floating gate 14 or by erasing electrons or holes from floating gate 14. Meaning, since floating gate 14 is completely separated by tunnel oxide film 12 and dielectric film 16, e.g., an Oxide+Nitride+Oxide (ONO) dielectric film, electrons or holes injected into floating gate 14 do not escape floating gate 14 even if power is not supplied, such that data is not lost. For data storage or erasure, a bias applied to an externally accessible terminal, i.e., control gate 18 and the junction or substrate 10 can be induced to floating gate 14, so that a large electric field can be formed between both ends of tunnel oxide film 12.
A ratio of the voltage applied to control gate 18 and the junction or substrate 10 and induced to floating gate 14 is referred to as a coupling ratio (CR). As the coupling ratio is large, efficiency of programming and erase operations for cells can increase, and a voltage applied from the outside can be lowered. Meaning, control gate 18 is an electrode that functions as a gate of a nonvolatile memory having a polysilicon stacked structure. Programming and erasure for cells are performed according to the bias state of this electrode. Generally, after such a gate is etched, the dielectric film is etched.
A process for manufacturing such a semiconductor flash memory is described as follows. First, tunnel oxide film 12 and polysilicon for floating gate 14 are deposited on and/or over semiconductor substrate 10. A silicon nitride film, e.g., tetraethylorthosilicate (TEOS) layer is etched. Polysilicon is then deposited on and/or over the polysilicon for floating gate 14 to form control gate 18, and then a control gate pattern is formed. Control gate 18 is etched so that spacer 22 is formed by an etch-back effect. Polysilicon is etched by using an etching selectivity of an oxide film and polysilicon. When spacer 22 is removed, the underlying oxide film and nitride film are removed. In this case, an ONO step is formed between two layers of polysilicon. Finally, ONO is etched again to remove the ONO at sidewall.
In this way, in the flash memory cell, programming or erasure is performed in accordance with presence/absence of electrons in the floating gate on the gate oxide film. The floating gate is insulated by the ONO structure or a similar structure, and the control gate is deposited as an upper electrode. Programming or erasure of cells is determined by the bias applied to the control gate. To increase the operation speed of such a flash memory cell, it is necessary to reduce a cell size, but it is difficult to reduce the cell size since a general transistor is used, as illustrated in FIG. 1. Nevertheless, it is very important to reduce the area of the flash memory cell for increasing the entire memory density and the memory operation speed thereby enhancing memory performance.